The invention relates generally to the field of multiple microprocessor watchdog systems in which software and/or hardware is provided to monitor system operation and implement microprocessor resets in the event of improper system operation.
In prior microprocessor systems, it is known to have an external watchdog or activity detector circuit which monitors an output of a microprocessor and resets the microprocessor if improper microprocessor operation is determined. Typically the watchdog, or activity detector, circuit makes this determination by noting that the microprocessor has not produced an expected output within a predetermined time interval. Such watchdog circuits are known and commonly utilized to reset a microprocessor when the microprocessor has failed to produce an expected output.
In some prior systems, it is desirable to utilize two separate microprocessors, with one of them comprising a main microprocessor performing a number of complex time-consuming functions, and another comprising a less complex microprocessor performing relatively simple functions while receiving and processing output information supplied by the main microprocessor. Such systems can be utilized in providing a visual display output. In these systems the main microprocessor receives a number of sensor inputs, and provides a number of various outputs, as well as a stream of data to a second microprocessor. The second microprocessor formats the data of the first microprocessor and provides the formatted data to a visual display device In such systems, two microprocessors are utilized because the formatting task, while relatively straightforward, cannot be included in the main microprocessor program without unduly slowing down the operation of the main microprocessor. Thus, two microprocessors are utilized.
In multiple microprocessor systems such as those discussed above, it would be desirable to monitor the operation of each of the microprocessors and generate resets for these microprocessors in response to various failure modes. Of course, each microprocessor could utilize its own separate watchdog circuit to monitor the output of that microprocessor, but this would be a costly alternative, and would not insure proper synchronous operation of the microprocessors when one of the microprocessors was reset, but the other was not. In some multiple microprocessor systems, it has been proposed to utilize a single watchdog or activity detector to essentially monitor the operation of an initial microprocessor which provides data to a subsequent microprocessor. In such a system, each of the microprocessors was reset by a single external watchdog circuit monitoring an output of the initial microprocessor. In addition, the initial microprocessor could also separately reset the subsequent microprocessor under some conditions. However, in such a system, the operation of the subsequent microprocessor was not monitored, and some failures in the operation of the subsequent microprocessor would not result in a resetting of the system while insuring proper synchronous operation of the initial and subsequent microprocessors after reset.